The following sampling erase test is proposed as a semiconductor memory erase test. In this sampling erase test, the number of erase pulses by which erase is completed for a part of memory cells in a memory cell array is found and erase is performed in a remaining area on the basis of the number of erase pulses.
The following erase test method is proposed as an EEPROM (Electrically Erasable Programmable Read-Only Memory) erase test method. In this erase test method, an erase test is repeated in a part of a storage area until the determination that erase is performed normally is made, the width of an erase pulse is set on the basis of the number of repetitions, and an erase test is performed in a remaining large part of the storage area by the use of the pulse width.    Japanese Laid-open Patent Publication No. 08-31189    Japanese Laid-open Patent Publication No. 2000-207897    Japanese Laid-open Patent Publication No. 2001-273792
It is assumed that the number or width of erase pulses obtained by performing an erase test in a part of a storage area is considered as a verification threshold at the time of performing verification in a remaining part of the storage area. If erase is completed for a memory cell before this verification threshold is reached, then the determination that the memory cell is normal is made.
There may be a memory cell in a part of a storage area which needs a long time for erase, compared with the other memory cells. In this case, the number or width of erase pulses obtained is influenced by the memory cell. As a result, a verification threshold becomes high and a verification standard is relaxed at the time of performing verification in a remaining part of the storage area. In this case, a memory cell which is originally bad cannot be detected and the reliability of a semiconductor memory decreases.